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Sega Saturn SCSP: Sound Slots, Shared RAM, and Effects-DSP Routing

Follow Saturn SCSP sound through 32 programmable slots, shared sound RAM, the sound CPU, DSP sends, memory arbitration, and testable timing.

The Sega Saturn’s sound block is a subsystem, not a single sample player. It combines a sound CPU, the SCSP custom sound processor, and 4 megabits (512 KiB) of sound RAM. The SCSP has 32 sound generators, a digital mixer, timers, interrupt facilities, and an effects DSP. The sound CPU can run independently of the main SH-2 CPUs, while the main system can also access sound registers and memory through the system bus. Accurate sound therefore depends on ownership, data lifetime, slot state, and event timing as much as on the final audio waveform.

The SCSP should not be conflated with the Saturn’s separate SCU DSP. The SCSP DSP processes sound/effects routing; the SCU’s DSP is a different system-level processor. Clear naming in traces and code avoids assigning audio effects to the wrong unit.

A slot is a stateful voice, not just an address

Each of the 32 SCSP slots has registers describing its source and playback behavior. Depending on configuration, a slot can operate in PCM or FM-related mode, with parameters for start and loop addresses, pitch, level, pan, envelope, modulation, and key control. The engine advances slots over time and mixes them; a slot’s output depends on the current envelope and modulation state, not only on the sample byte at the current address.

The sound CPU typically manages sequencing and updates slot state, while waveform and program data reside in sound RAM. This division matters in an emulator: a sound driver write is a timed register event. Applying all writes at the end of a host audio block can move key-on, pitch, and envelope changes by thousands of emulated samples. Schedule register writes at the event time or use a synthesis architecture that can split the block at each write.

Loop modes must preserve their address and direction semantics. A normal loop, reverse loop, or ping-pong loop cannot be modeled by simply wrapping an integer cursor at one end. Pitch and sample format affect how the cursor advances, while interpolation and envelope behavior affect the output. Keep the emulated sample address in the console’s fixed-point representation and translate to a host index only at the memory-fetch boundary.

Sound RAM is shared across several clients

The 512 KiB sound RAM stores sound CPU code, sequence and waveform data, and delay/effect buffers. The SCSP, sound CPU, and main system can all access it, but their address views and permitted access widths are not necessarily identical. The Sega manual warns that some register classes are read-only or write-only and describes access restrictions for main-side byte accesses. Implement each bus master against the documented map instead of exposing one unconstrained host pointer.

Memory is also a scheduled resource. The SCSP sound source section and DSP need cycles, and CPU/DMA traffic must coexist with sample fetch and effects processing. The sound manual documents cycle allocation for slot access, which means a bulk copy by one CPU cannot be treated as invisible to the audio engine. If an emulator models contention approximately, state that clearly and add tests proving that ordinary operation remains deterministic; do not claim cycle accuracy unless arbitration has been implemented and compared.

The main CPU’s access to the sound block crosses the SCU bridge. A main-side write to sound RAM or SCSP registers may be queued or incur bus timing different from a sound-CPU-local write. Trace the issuing processor, address view, access width, and emulated cycle. This often explains why audio drivers use a command buffer or semaphore instead of having the main game thread rewrite every voice directly.

Effects DSP and mixer are downstream stages

The SCSP effects DSP can combine selected slot signals and apply sound-field effects using a programmable processing sequence and delay storage. The slot-to-DSP send configuration determines which sources participate. The final mix also includes level and pan choices and can receive external digital audio input such as CD-DA. Keep the path from source slot through sends and DSP to output observable as separate stages.

A wrong reverb tail may be caused by delay-buffer addressing or DSP program state, not by the sample decoder. A wrong channel balance may be a pan, level, or mixer problem. A missing sound after a scene transition may be a sound-CPU handshake, slot key-off, or DMA problem. Capture per-slot state and DSP input/output checkpoints before replacing the whole subsystem with a generic reverb plug-in.

Do not conflate the Saturn’s external CD-DA path with PCM samples already stored in sound RAM. Both can be mixed, but their timing and source state differ. For reproducible output, the CD reader, sound CPU, slot generator, DSP, mixer, and host resampler need an explicit clock-domain policy. A host output callback must never become the authoritative clock for guest slot advancement.

A complete diagnostic snapshot

At a chosen emulated time, record all slot registers, current sample addresses, envelope level/state, key state, loop state, sound RAM page hashes, sound-CPU PC and pending interrupt, timer state, DSP program counter and delay buffer indices, external input level, and mixer output. Preserve raw values as well as human-readable interpretations. For a minimal test, configure a single slot with a known waveform and envelope, then add a loop, modulation, second slot, and DSP send one at a time.

Use a structured test manifest so a result is repeatable:

{
  "sample_rate": 44100,
  "active_slots": [0],
  "sound_ram_sha256": "record-the-fixture-hash-here",
  "events": [
    {"cycle": 0, "event": "write_slot_state"},
    {"cycle": 128, "event": "key_on"}
  ]
}

The hash placeholder must be replaced by a measured fixture digest; this example is a schema, not captured Saturn output. Compare output samples or selected internal checkpoints against a trusted implementation and document the sample phase and host rate. Do not compare only a compressed recording, where resampling and encoding can mask single-cycle differences.

Validation plan

Test each slot’s key-on/off, envelope stages, pitch increments, sample boundaries, loop types, pan, level, and format. Then test two slots mixed together, a DSP send, a delay buffer wrap, sound-RAM access by each bus master, DMA overlap, timer interrupts, and sound-CPU/main-CPU synchronization. Use silence, impulse, ramp, and periodic waveform fixtures so address and interpolation errors are distinguishable from effects errors.

Save states must include slot cursors and envelopes, sound CPU state, RAM, DSP internal registers and delay history, timers, interrupt latches, pending bus transactions, and resampler state. Restoring only RAM plus voice registers yields a discontinuity because the DSP and envelopes have temporal memory.

The SCSP’s strength comes from its many cooperating parts. Model the slot engine, shared memory, sound CPU, effects DSP, and mixer as one timed subsystem with explicit interfaces, then validate each interface in isolation before judging the musical result.

Sound-driver scheduling is an important integration test. A command can be written by the main CPU, copied through a shared buffer, interpreted by the sound CPU, and applied to one or more SCSP slots. If the emulator lets the sound CPU inspect a partially written command or applies a key-on before the associated sample address has been published, the defect may sound like random noise rather than a clean protocol error. Capture producer and consumer indices, command bytes, ownership changes, and the exact slot-register writes. Verify that wrapping the command buffer cannot make old data appear new, and that a sound CPU interrupt does not acknowledge unrelated SCSP causes. Compare the resulting event stream with a known-good run before comparing PCM output. This separates driver handshake errors from synthesis arithmetic and makes the sound block approachable even when a title uses a complex proprietary sequencing format.

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