tag
30 posts
Use the Linux DMA API correctly by separating CPU and device addresses, mapping lifetimes, cache coherency, scatter-gather paths, and teardown.
Trace Linux page-pool allocation and recycling across NAPI, skbs, XDP, and DMA while preserving references, sync ranges, and teardown safety.
Model Amiga blitter DMA precisely: derive raw minterms, preserve overlapping copies with descending mode, honor word masks and modulos, and test completion safely.
Trace Amiga Paula audio from chip-RAM DMA through channel reloads and period timing, with practical emulator state, trace, and regression-test boundaries.
Understand Atari 7800 MARIA display-list DMA, line RAM construction, CPU stalls, graphics modes, and the timing evidence accurate emulation requires.
Understand ANTIC as a display-list processor with independent list and screen pointers, LMS fetches, scroll modifiers, display-list interrupts, and cycle stealing.
Separate GameCube DSP program and data memory from ARAM sample storage, then trace bootstrap, mailbox handshakes, DMA, and audio-state diagnostics.
Model the N64 Audio Interface as a clocked PCM DMA endpoint, from aligned RDRAM buffers and a two-entry queue to status transitions and sample-rate divisors.
Separate Nintendo DS PCM channels from ARM7 sound FIFOs, then trace FIFO requests, capture routing, DMA writes, and audio-clock edge cases.
Model PS1 DMA as seven timed channel engines with DPCR priority, synchronization modes, chopping windows, linked lists, and latched DICR flags.
Trace the PlayStation MDEC decode pipeline from command and quantization tables through macroblock conversion, FIFO flow, and DMA completion.
Trace PlayStation 2 IPU command words, bitstream buffering, MPEG macroblock work, and DMA completion without confusing decoded pixels with GS output.
Follow PS2 SIF commands and RPC data across the Emotion Engine and IOP, including DMA completion, cache writeback, server dispatch, and reply lifetime.
Understand PS2 VIF and GIF as separate transfer stages, from DMA tags and vector unpacking to GS paths, stalls, and completion interrupts.
Follow Saturn CD sectors through FAD ranges, masked subheader filters, selector connections, partition buffers, DMA, and transfer completion.
Trace the SNES SA-1's two CPU views, shared work RAM, interrupt flags, arithmetic hardware, DMA paths, and deterministic bus-visible synchronization.
Apply the original PC/AT DMA controller's 64 KiB and 128 KiB page constraints when allocating, programming, and validating DOS driver buffers.
Implement a bounded Sound Blaster playback lifecycle by probing DSP status, configuring DMA and IRQ ownership, acknowledging completion, and cleaning up.
Use DOS Virtual DMA Services to validate physical contiguity, honor DMA boundaries, manage bounce buffers, and unlock memory after transfers.
Operate FreeBSD DMA for local system mail and outbound relay delivery with credential-safe configuration, queue checks, testing, and failure triage.
Trace Amiga Copper MOVE, WAIT, and SKIP instructions alongside bitplane DMA, Chip RAM fetches, bus slots, and safe display-list validation.
Trace Game Boy OAM DMA from the FF46 register to sprite memory, and understand why CPU bus restrictions and timing belong in the emulated hardware model.
Implement CGB VRAM DMA accurately by separating general-purpose and HBlank transfers, preserving bank state, and testing FF51-FF55 timing and status.
Configure GBA DMA with correct channel priority, immediate and video triggers, address modes, sound FIFO bursts, and measurable emulator tests.
A hardware-grounded guide to Mega Drive VDP DMA modes, 68000 bus stalls, FIFO status, display-time limits, and emulator validation.
A production-minded guide to Nintendo 64 DMA cache maintenance, writeback and invalidation order, cache-line alignment, and emulator regression tests.
Trace NES DMC sample fetches, APU frame events, OAM-DMA contention, and controller-read glitches with cycle-aware emulator models and tests.
Understand how the PC Engine HuC6270 stages sprite attributes in VRAM, copies them to internal SATB, and reports DMA completion to software.
Read the Saturn SCU DMA contract: three CPU transfer levels, direct and indirect modes, byte counts, address updates, triggers, and documented restrictions.
Understand SNES horizontal-blank DMA table entries, transfer patterns, channel state, and the VBlank discipline needed for deterministic raster effects.