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10 posts
Model Game Boy APU frame-sequencer clocks, channel timers, sweep overflow, length counters, and envelope updates with hardware-aware tests.
Model the Game Boy Camera as a banked cartridge peripheral, including busy handshakes, sensor registers, RAM visibility, image processing, and capture tests.
Implement the Game Boy MBC3 real-time clock accurately: bank selection, snapshot latching, halt and carry bits, 512-day rollover, and regression tests.
Model Game Boy channel 3 as a 32-nibble sequencer with model-specific wave RAM arbitration, DAC level, trigger state, and testable sample timing.
Read Game Boy buttons correctly through FF00 by scanning its active-low matrix, handling selection-induced edges, debouncing input, and testing joypad interrupts.
Trace Game Boy OAM DMA from the FF46 register to sprite memory, and understand why CPU bus restrictions and timing belong in the emulated hardware model.
Implement Game Boy link transfers with correct SB and SC semantics, clock ownership, CGB rates, interrupt handling, synchronization, and bounded failure recovery.
Model the Game Boy's combined STAT interrupt line and LY-to-LYC coincidence correctly, then debug raster effects across scanlines and hardware revisions.
Model the Game Boy's hidden divider, falling-edge timer input, DIV/TAC write effects, delayed TIMA reload, and model-specific validation boundaries.
Implement Super Game Boy commands with correct JOYP pulse encoding, packet framing, transfer delays, multiplayer requests, and emulator validation.