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Sega Genesis YM2612 Channel 3 Special Mode: Four Frequencies, One FM Channel

Decode YM2612 register 27h special mode, map channel 3 operator frequencies, preserve timer controls, and test key-on and frequency-latch behavior.

The Sega Genesis/Mega Drive’s YM2612 has a special mode in which channel 3 can assign a separate frequency value to each of its four FM operators. It is a subtle extension to the normal FM channel model: the operators still belong to one channel and remain connected by the selected modulation algorithm, but they no longer all derive their pitch from the channel’s single shared frequency register pair.

That distinction matters in a synthesizer, a sound driver, and an emulator. Treating special mode as “four extra channels” exaggerates what the chip provides. Ignoring it and always using the shared channel 3 frequency makes valid register streams sound wrong. Correct support requires decoding the mode field, reading the special frequency registers in the right order, and preserving the timer-control bits that share the same mode register.

Register 27h combines separate controls

YM2612 register 27h contains two unrelated groups of controls. Bits 7–6 select the channel 3 mode; bits 5–0 control timer A and timer B load, enable, and flag-reset behavior. For channel 3 special-frequency mode, the documented value of the two mode bits is 01 (bit 6 set, bit 7 clear). The timer controls must not be confused with the mode selection just because they occupy the same register.

This creates a practical driver rule: keep a shadow value for the control bits the sound driver owns, or use a carefully defined update routine that preserves unrelated timer configuration. Writing a constant such as 0x40 to select special mode also clears the lower timer controls. That may be harmless in a simple test with timers unused, but it is not safe as a general update strategy in software that shares the chip with a music driver or interrupt routine.

Register field Bits Role
Channel 3 mode 7–6 Normal or special frequency arrangement
Timer B reset/enable/load 5, 3, 1 Timer B flag and operation controls
Timer A reset/enable/load 4, 2, 0 Timer A flag and operation controls

The documented 01 mode is the one relevant to independent channel 3 operator frequencies. Do not infer undocumented behavior for other two-bit combinations from the special-mode case; emulate or use only combinations supported by the hardware reference and the intended chip variant.

Four frequency pairs replace one shared pair

In normal mode, channel 3 uses the usual low and high frequency registers at A2h and A6h. In special mode, the first operator continues to use that pair, while the other three receive their own pairs. The mapping is not numerically ordered by every naming convention used for operator slots, so preserve the documented addresses instead of deriving them from a guessed channel index.

Frequency source Low register High register
Channel 3 operator 1 A2h A6h
Channel 3 operator 2 A8h ACh
Channel 3 operator 3 A9h ADh
Channel 3 operator 4 AAh AEh

Each frequency value is assembled from a low byte and a high register containing the remaining frequency bits plus the block (octave) field. Software should write the high portion before the low portion; the register reference describes the new frequency taking effect on the low-byte write. An emulator should model that commit boundary rather than recomputing the effective frequency after every half-register write.

set_frequency(low_reg, high_reg, block, fnum):
    write(high_reg, (block << 3) | ((fnum >> 8) & 0x07))
    write(low_reg, fnum & 0xFF)  // completes the frequency update

This is register-packing pseudocode; a real driver must also account for the YM2612’s address/data port protocol and the selected register bank. The code intentionally takes the register addresses as parameters. In channel 3 special mode, using a normal channel frequency helper that always writes A2h/A6h will accidentally retune operator 1 repeatedly instead of programming four distinct pitch values.

Independent pitch does not bypass FM routing

Special mode changes the frequency source for the operators. It does not replace the channel’s four-operator synthesis path, algorithm selection, feedback behavior, envelope parameters, stereo routing, or key-on control. The algorithm still determines which operators modulate other operators and which operator outputs contribute to the channel signal.

As a result, four stored frequency values do not guarantee four audible notes. A frequency assigned to an operator that is currently acting as a modulator changes the modulation applied downstream; it does not necessarily produce an independent carrier tone. Some algorithms expose multiple carrier outputs, but the channel remains one synthesis block with shared channel-level state. A tracker or driver may exploit the arrangement for unusual timbres, dissonant modulation, or layered pitch behavior, yet should document the algorithm and key state that make those frequencies audible.

The YM2612 key-on register 28h encodes the channel and a four-bit operator mask. Channel 3 is selected with the channel code 010 in bits 2–0; bits 7–4 select the operators. Since the operators can be keyed individually, special mode can be tested with one operator enabled at a time. However, a clean test must also set an algorithm in which the chosen operator’s contribution is observable; otherwise a silent result may be caused by FM routing, not incorrect frequency decoding.

Keep mode transitions and writes deterministic

A good implementation keeps both raw register state and derived oscillator inputs. When register 27h changes, update the mode state but retain timer state. When a frequency high-byte write arrives, stage the high portion; when the associated low-byte write completes the pair, commit the new effective frequency for the relevant operator. The normal mode should continue to use the shared pair for all channel 3 operators, while special mode selects the separate pairs for that channel only.

Do not apply the mapping to channel 6. Although it is a paired channel in other parts of the YM2612 register layout, the special-frequency arrangement documented here applies to channel 3. Also keep register bank selection separate from operator selection: the YM2612 has two register banks, with channels 1–3 in one and channels 4–6 in the other. A correct operator table used against the wrong bank is still a broken implementation.

If the emulator uses a save state, preserve the raw 27h value or equivalent mode and timer state, all relevant high/low frequency register values, and the committed oscillator frequencies. Capturing only a synthesized phase increment can lose a partially written high/low pair. Restoring mid-write should follow the same hardware-visible transition as an uninterrupted register stream.

Regression tests for mode and slot mapping

Build a register-level fixture with distinct frequency values for the four special-mode pairs. Enable special mode, select an algorithm with observable outputs, key operators individually and in combinations, and compare each resulting pitch behavior against a trusted chip reference or hardware capture. A test that assigns the same value to all four pairs cannot detect address swaps.

Then test the state transitions:

  1. Start in normal mode and verify that A2h/A6h controls all four channel 3 operators as documented.
  2. Set special mode while preserving the chosen timer bits in 27h.
  3. Write different high/low pairs and verify the correct operator changes only after the low-byte commit.
  4. Change one operator’s frequency and confirm the other three do not move.
  5. Return to normal mode and confirm the shared frequency path is used again.
  6. Save and restore between the high and low writes, then compare the resumed trace with an uninterrupted trace.

Test the timer controls independently while special mode is active. This catches a common register-shadow bug in which mode changes disable timer flags or accidentally restart a timer. Keep the test fixture’s 27h values explicit and assert both the mode bits and timer bits after every write.

Finally, compare sound only after register-level behavior is correct. FM envelopes, algorithm routing, panning, analog output, chip revision, and the Mega Drive’s YM2612 clock all affect the waveform. A spectral difference alone does not prove the special-mode mapping is wrong. Save the register trace, chip variant, clock assumptions, algorithm, operator configuration, key events, and sample capture together so the failure can be reproduced rather than tuned by ear.

Channel 3 special mode is a focused extension, not a second four-voice synthesizer hidden inside the YM2612. Model it as four operator-specific pitch sources feeding the existing channel architecture. That precise mental model keeps the address map, write timing, timer behavior, and audio routing testable as separate parts of the emulated device.

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