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Cartridge Mappers and Bank Switching: How Consoles Addressed Games Larger Than Memory

A hardware-grounded guide to cartridge address decoding, PRG and graphics banks, mapper registers, mirroring, IRQs, save memory, and emulator tests.

Many cartridge consoles expose a CPU address space far smaller than the total ROM in later games. Cartridge hardware solved the mismatch by decoding writes to control registers and mapping selected chunks—banks—into one or more visible address windows. The “mapper” is therefore active hardware behavior, not merely a ROM-size field in a file header.

Address windows make storage visible in pieces

Suppose a CPU can see a 32 KiB cartridge window while the board contains 256 KiB of program ROM. The mapper can keep one 16 KiB bank fixed at the reset-vector end and switch another 16 KiB bank in response to a register write. Game code calls common routines in the fixed bank and selects level or graphics code into the variable bank.

A mapping formula needs explicit units and masks:

bank_count = rom_size / bank_size
selected = register_value & implemented_bank_bits
physical = selected * bank_size + (cpu_address - window_base)

Real boards may ignore high bits, force particular bits, wrap out-of-range selections, split windows more finely, or apply mode-dependent formulas. An emulator must implement what the board decodes, not sanitize every register to a mathematically convenient modulo.

Program ROM is only one dimension. Mappers can bank character ROM or RAM for graphics, control name-table mirroring, expose battery-backed RAM, protect writes, latch bus values, and generate scanline or cycle-based interrupts. On some platforms, an on-cartridge coprocessor or audio hardware extends the console substantially.

Register timing is observable

Writes that select a bank happen at a precise CPU time. If the CPU fetches its next instruction from the switched window, the new mapping must be visible at the hardware-defined moment. Deferring mapper updates until the end of a frame breaks code that switches data mid-routine or graphics during rendering.

Bus conflicts are another board property. On boards without hardware that cleanly isolates ROM output during a register write, the value seen on the bus can combine the CPU’s value with the ROM byte at that address. Games may deliberately choose register-write addresses whose ROM contents produce the intended bits. Treating every write as conflict-free can select the wrong bank.

IRQ mappers require the clock source documented for that board. A counter described loosely as “scanline” may really observe PPU address transitions, filtered edges, CPU cycles, or an external clock. Updating once per rendered line may pass simple games and fail split-screen timing.

File metadata identifies a board imperfectly

Dump formats usually store a mapper or board identifier plus ROM/RAM sizes and region data. Old headers can be ambiguous, truncated, or incorrectly assigned. Database corrections and extended header formats exist because a numeric mapper family may contain submappers with different wiring.

Preserve the original dump and hash before editing metadata. Compare against a trusted preservation database, inspect known board markings when lawful and safe, and keep the correction as sidecar metadata or a reproducible header transformation. Renaming a file to match a guessed board does not change its electrical behavior.

Test each independent behavior

Build mapper tests that select first, middle, last, masked, and invalid banks; change modes; write-protect RAM; power-cycle persistence; alter mirroring; and exercise IRQ acknowledgement. Run instruction-level tests around a bank-switching write and trace CPU/PPU addresses. Compare against hardware test ROM results or verified documentation, not only one commercial title.

A mapper implementation is correct when address decoding, timing, writable state, and board variants agree. Thinking of it as “load a larger ROM” loses exactly the hardware details that allowed the larger game to exist.

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