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Game Boy MBC1: Why Bank Zero, Mode One, and Cartridge Wiring Matter

Trace MBC1's two ROM windows, RAM gate, secondary bank register, and mode-dependent mapping without treating every MBC1 cartridge as the same geometry.

An original Game Boy CPU can address a 32 KiB cartridge ROM window, but many games need more storage. MBC1 puts bank-selection logic in the cartridge, not in the console. Reads from $0000–$7FFF fetch ROM; writes to portions of that same address range control the cartridge’s banking registers. That dual use is the first trap for an emulator or homebrew program: a write to $2000 does not edit ROM byte $2000; it changes which ROM bank appears in the switchable window.

Pan Docs describes a family of MBC1 wiring arrangements, not one unlimited bank register. A normal small-ROM cartridge, a large-ROM cartridge, a 32 KiB-RAM cartridge, and an MBC1M compilation cartridge can make the same register write lead to different visible bytes. Before debugging a supposed bank-switch failure, identify the cartridge geometry and wiring. This article uses Pan Docs’ register names and hexadecimal Game Boy addresses. It does not claim that these rules apply to MBC2, MBC3, MBC5, or every clone cartridge.

Two ROM windows, one often fixed

The lower ROM window, $0000–$3FFF, normally exposes the first 16 KiB, bank $00. The upper window, $4000–$7FFF, exposes a selected 16 KiB bank. On power-up the MBC1 registers default to zero, but the five-bit ROM-bank register’s zero is treated as one for the upper window, so bank $01 appears there by default. That special case prevents simply writing zero to show bank zero in both windows on a normal MBC1 cartridge.

Writes to $2000–$3FFF set the lower five bits of the switchable ROM bank. Higher input bits are discarded. If the register’s five-bit value is zero, MBC1 translates it to one before forming the upper-window bank. On a large, conventionally wired ROM, a secondary two-bit value from writes to $4000–$5FFF supplies the upper bank bits. The effective upper-window selection is therefore the secondary value shifted by five, plus the translated lower value. Trying to choose bank $20 by setting the secondary register to one and the lower register to zero gives $21; the same issue occurs at $40 and $60.

There is a subtle exception on smaller ROMs. Pan Docs notes that the zero-to-one test examines the full five-bit register even when the ROM chip has fewer address lines and masks away high bank bits. For a 256 KiB ROM, writing $10 to the lower register can therefore avoid the zero translation while the actual ROM addressing ignores that fifth bit, exposing bank zero in the upper window. That is a hardware-selection consequence, not a portable way to request bank zero across all MBC1 cartridge sizes. An emulator that applies a single modulo operation before the zero translation can get this edge case wrong.

RAM is gated separately from bank choice

If the cartridge includes external RAM, the $A000–$BFFF window accesses it. A write to $0000–$1FFF whose low nibble is $A enables RAM; another low nibble disables it. Pan Docs recommends disabling RAM after use to reduce accidental corruption during power-down or removal. If RAM is disabled, writes to that window are ignored and reads return open-bus values, often $FF but not guaranteed. An emulator should not hard-code the observation $FF as proof of a missing save file.

The cartridge may have 8 KiB of RAM in one bank, or 32 KiB in four 8 KiB banks. Pan Docs says the 32 KiB arrangement is available only with ROM sizes no larger than 512 KiB in the standard wiring. A large 1 MiB-or-more ROM uses the two-bit secondary register as extra ROM address bits, at the cost of fixed 8 KiB RAM. Thus “MBC1 supports 2 MiB ROM and 32 KiB RAM” describes separate maxima, not a single conventional cartridge combining both. The RAM enable gate remains distinct from selecting a RAM bank.

Mode one changes the lower window

Writes to $6000–$7FFF select the banking mode: zero for simple mode, one for advanced mode. In simple mode, the lower ROM window and RAM window are locked to bank zero, while the secondary register still contributes to the upper ROM bank on a large-ROM cartridge. In advanced mode, the secondary register can switch the lower ROM window and, on the RAM-wired arrangement, the RAM bank. If neither the ROM nor RAM is large enough to use the secondary register, changing mode has no observable effect.

This explains how a large ROM reaches its otherwise inaccessible $20, $40, or $60 banks: in advanced mode they appear in the lower window, rather than in the ordinary upper window. It also explains the risk to running code. Interrupt vectors and handlers traditionally occupy the beginning of ROM; changing the lower window without arranging valid vectors and code in the new bank can make the program jump into the wrong bytes. A development tool should display both window mappings, not merely a single “current ROM bank” value.

Pan Docs identifies a further MBC1M multi-game wiring. Here the secondary register contributes bits four and five rather than five and six, and the top bit of the main bank register is ignored for ROM addressing. In advanced mode the lower window can become $00, $10, $20, or $30, letting a compilation cartridge select a game’s base bank. Ordinary large-ROM MBC1 would instead use $00, $20, $40, or $60. Do not infer MBC1M solely from a ROM size header; examine the actual image and wiring evidence before applying the variant formula.

A small, deterministic emulator check

Build a synthetic test ROM with a different marker byte in each 16 KiB bank, if your emulator test harness supports such images. Keep the test in an emulator or disposable test cartridge; do not write to an original cartridge. With default registers, read one marker in each ROM window. Then write one to $4000 and zero to $2000: on a conventionally wired large MBC1 ROM, the upper window should identify bank $21, not $20. Switch to mode one by writing one to $6000 and inspect the lower window; it should now identify bank $20. Restore mode zero and check that the lower window returns to bank zero. On a RAM-wired test image, enable RAM explicitly, select a RAM bank in advanced mode, and verify that a disabled gate blocks writes.

Those are proposed tests, not results obtained here. Their value is that each observation distinguishes one mapping rule: the zero translation, the secondary register, the mode switch, and the RAM gate. Recording cartridge size and MBC1 versus MBC1M wiring alongside a failure is as important as recording register values. Without that boundary, two correct cartridges can look contradictory.

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